A two-floor parking garage controller designed and simulated in Verilog on the Xilinx Basys 3 FPGA. The design uses flip-flop-based sequential logic to track occupancy and a finite state machine to handle entry and exit, with a multiplexed seven-segment display showing real-time floor counts. Verified in Vivado simulation with testbenches, then deployed and validated on the physical board.
Synchronizing entry and exit sensor inputs without race conditions, debouncing physical switch signals, and driving a multiplexed seven-segment display without visible flicker while keeping occupancy counts accurate in real time.
Designed a finite state machine to sequence entry/exit transitions cleanly, used flip-flop-based registers to hold occupancy counts per floor, and implemented a clock-divided multiplexing scheme to refresh the seven-segment display fast enough to appear flicker-free.
Verified correct FSM behavior and occupancy tracking through Vivado testbenches, then confirmed matching real-time behavior on the physical Basys 3 board.
- FSM-driven entry/exit handling
- Flip-flop-based occupancy counters per floor
- Multiplexed seven-segment display output
- Vivado simulation with testbenches
- Deployed and validated on physical FPGA hardware
