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EngineeringIoTIn progress

Hardware-in-the-Loop Signal Processing Pipeline

Built a real-time Python WebSocket dashboard visualizing raw vs. HDL-filtered sensor telemetry.

Hardware-in-the-Loop Signal Processing Pipeline preview

Engineered a Hardware-in-the-Loop signal processing pipeline on a custom Buildroot Linux system (Raspberry Pi 5), running Verilator-compiled VHDL FIR filter modules against live accelerometer and temperature data streamed from an ESP32 FreeRTOS node over UART. Implemented automated RTL regression testing via GitHub Actions CI/CD, replicating pre-silicon verification workflows. Built a real-time Python WebSocket dashboard visualizing raw vs. HDL-filtered sensor telemetry.